The goal of this thrust is to develop analytical models and metrics to demonstrate the superiority of disaggregated memory systems over conventional systems for several classes of computational workflows that benefit from access to larger memory pools with higher bandwidth but also with higher latency. 

We also aim to develop tools for empirical evaluation of prototypical disaggregated memory systems and to simulate performance analysis of system designs for real-world workflows.

Publications

Developable A., M. Halappanavar, A. Puri, V. Narayanan, and A. Marquez.  “Using Isoefficiency as a Metric to Assess Disaggregated Memory Systems for High Performance Computing.” In proceedings of the 10th International Symposium on Memory Systems (MEMSYS 2024), Melrose Georgetown Hotel - Washington D.C. Sept 30-October 3, 2024.

Abstract: Memory disaggregation is an approach to decouple compute and memory to minimize the total cost of ownership. However, analytical methods to study the impact of this approach are not readily available for high performance computing use cases. In this position paper, we propose isoefficiency as an approach to analytically demonstrate the classes of algorithms that would benefit from disaggregated memory technologies as we scale to a larger number of processors. Isoefficiency of an algorithm is given by a function 𝑁(𝑝) that measures the degree to which the problem size needs to increase with 𝑝 (number of processors) to maintain a constant efficiency. We evaluate isoefficiency using sparse general matrix–matrix multiplication (SpGEMM) on a 2-socket shared memory system and the simulation of a CXL-based disaggregated system. Our results support the suitability of isoefficiency for evaluating disaggregated memory systems with different design choices in conjunction with different application kernels.