PNNL

Scientists and engineers at PNNL draw on signature capabilities in chemistry, Earth sciences, and data analytics to advance scientific discovery and create solutions to the nation's toughest challenges in energy resilience and national security. We’re looking for motivated candidates in the areas of data science, high-performance computing, cybersecurity, software engineering, and computational mathematics and statistics to join our teams. 

Let's talk!

Stop by our booth (#4856) and learn more about what it's like working for a national laboratory and the exciting scientific breakthroughs happening at PNNL. We’re hiring for a variety of positions and building teams that have never been built before. Meet PNNL engineers, scientists, researchers, managers, and recruiters who can tell you what positions are available and how you can help us change the world!

We will also be at the Department of Energy booth (#1600). PNNL Chief Scientist for Computing Jim Ang will be giving at talk on November 15th at 1:45 p.m. on New Horizons for HPC. 

We're hiring!

 Check out our featured jobs!

• AI and Data Analytics PhD Intern - National Security Internship Program
• AI and Data Analytics Masters Intern - National Security Internship Program
• AI and Data Analytics Post-Bachelor Research Assistant - National Security Internship Program
• AI and Data Analytics - Undergraduate Tech Intern
• Undergraduate Intern - High Performance Computing
• Master's Intern - High Performance Computing
• PhD Intern - High Performance Computing
• Post Masters RA - High Performance Computing
• Post Doctorate RA - High Performance Computing
• Cloud Engineer 3
• Software Engineer 3
• Post Doctorate RA - Memory-centric Analysis and Optimization 
• Post Doctorate RA - Data-centric and Cloud-based Performance Modeling 
• Post Masters RA - Network Modeling and Analysis 

PNNL Speakers, Presentations, and Posters

Women in HPC: Diversifying the HPC Community and Engaging Male Allies Gokcen Kestor | Session organizer/presenter  November 13, 2022 Workshop | 8:30 a.m. – 5:00 p.m. CST | Presentation at 4:50 p.m. CST | C148 The twelfth international Women in HPC workshop will be held at SC22, Dallas, USA with the goal of celebrating success of women in HPC, recruitment and mentoring of women in the workforce. The WHPC workshop series has become the leading event on improving equity, diversity and inclusion, providing all attendees, irrespective of their gender, with the skills to thrive in the workplace and the information to build frameworks for diverse recruitment and retention policies and actions. Read more.

Towards Cross-Platform Portability of Coupled-Cluster Methods with Perturbative Triples using SYCL Ajay Panyala | Presenter/Contributor November 13, 2022 2022 International Workshop on Performance Portability and Productivity | 1:09 p.m. – 2:15 p.m. CST | C155 Tensor contractions form the fundamental computational operation of computational chemistry and more notably, these contractions dictate the performance of widely used coupled-cluster (CC) methods in computational chemistry. In this work, we study a single-source, cross-platform C++ abstraction layer programming model, SYCL for the application related to the computational chemistry methods such as CCSD(T) coupled-cluster formalism. An existing optimized CUDA implementation was migrated to SYCL to make use of the novel algorithm that provides tractable GPU memory needs for solving high-dimensional tensor contractions for accelerating CCSD(T). We present the cross-platform performance achieved using SYCL implementations for the non-iterative triples contribution of CCSD(T) formalism which is considered as the performance bottle neck on Nvidia A100 and AMD Instinct MI250X. Additionally, we also draw comparisons of similar performance metrics from vendor-based native programming models such as CUDA and ROCm HIP. Read more.

First Combined International Workshop on Interactive Urgent Supercomputing Vinay Amatya | Workshop Organizer November 14, 2022 Workshop | 8:30 a.m. – 12:00 p.m. CST | C148 Interactivity enables the exploitation of HPC in new and revolutionary ways, delivering many new and exciting opportunities for our community. Urgent computing is one example, where combining interactive computational modelling with the near real time detection of unfolding disasters can aid in urgently responding to real-world problems, ultimately saving lives and reducing economic loss. Whilst the importance of interactive and urgent workloads on HPC could be considerable for our community, supporting these requires expertise in a wide range of areas and the solving of numerous technical challenges. Read more.

Workshop on Artificial Intelligence and Machine Learning for Scientific Applications Gokcen Kestor | Session organizer/moderator November 14, 2022 Workshop | 1:30 p.m. – 5:00 p.m. CST | D220 Artificial intelligence (AI) is a game-changing technology that has shown tremendous advantages and improvements in algorithms, implementation, and applications. We have seen many successful stories of applying AI to scientific applications. However, there are a number of problems remaining to be studied to enhance the usability of AI in scientific applications. Addressing the above problems will bridge the gap between AI and scientific applications and enable wider employment of AI in HPC. The purpose of this workshop is to bring together computer scientists and domain scientists from academia, government, and industry to share recent advances in the use of AI in various scientific applications, introduce new scientific application problems to the broader community, and stimulate tools and infrastructures to support the application of AI in scientific applications. The workshop will be organized as plenary talks based on peer-reviewed paper submissions accompanied by keynotes from distinguished researchers and a panel discussion. Read more.

Towards Precision-Aware Fault Tolerance Approaches for Mixed-Precision Applications Bo Fang | Presenter Kevin Barker | Contributor Ang Li | Contributor November 14, 2022 12th Workshop on Fault-Tolerance for HPC at Extreme Scale | 3:54 p.m. – 4:09 p.m. CST | C143-149 Graphics Processing Units (GPUs), the dominantly adopted accelerators in HPC systems, are susceptible to a transient hardware fault. A new generation of GPUs features mixed-precision architectures such as NVIDIA Tensor Cores to accelerate matrix multiplications. While widely adapted, how they would behave under transient hardware faults remain unclear. In this study, we conduct large-scale fault injection experiments on GEMM kernels implemented with different floating-point data types on the V100 and A100 Tensor Cores and show distinct error resilience characteristics for the GEMMS with different formats. We plan to explore this space in the future by building precision-aware floating-point fault tolerance techniques for applications such as DNNs that exercise low-precision computations. Read more.

Data Lifecycles for Optimizing Data Movement Hyungro Lee | Presenter Jesun Firoz | Contributor Nathan Tallent | Contributor November 14, 2022 7th International Parallel Data Systems Workshop | 2:55 p.m. – 3:00 p.m. CST | C148 Scientific exploration is increasingly dependent on the convergence of scientific modeling, data analytics, and machine learning. The result is data-intensive workflows that are composed of multiple stages of computation and communication between distributed and heterogeneous computing resources. Data movement through storage systems is frequently the most significant bottleneck, which is compounded by increasingly large data volumes and rates. To identify opportunities for optimizing data movement, we are developing novel workflow telemetry that highlights data objects’ dynamic flow, reuse, lifetime, and locality. Our objective is to enable modeling and reasoning about task-data locality, especially compared to default placement and data exchange, and the scheduling of anticipatory data movement that selects what data should be staged in memory and when. Read more.

HPC Graph Toolkits and the GraphBLAS Forum Antonino Tumeo | Session Leader John Feo | Session Leader November 15, 2022 Birds of a Feather | 12:15 p.m. – 1:15 p.m. CST | C146 Government agencies, industry and academia are demanding a new generation of tools to efficiently solve large scale analytics problems in a variety of business, scientific and national security applications. This BoF gathers the community developing high-performance frameworks and workflows for large scale graph analytics to survey current approaches, identify new challenges and opportunities, and discuss interoperability of emerging infrastructures. A central goal is developing requirements and recommendations for future tools. As in previous editions, this BoF will explore, and compare and contrast conventional implementations as well as algebraic approaches, inviting the GraphBLAS community to discuss its state and evolution. Read more.

New Horizons for HPC Jim Ang | Speaker November 15, 2022 Talk | 1:45 p.m. – 2:30 p.m. CST | Booth #1600 High Performance Computing is entering an era that will require significant adaptations; fundamental technologies are changing, new models of computing are emerging, and traditional ecosystems are being disrupted. The speaker describes an open innovation model, guided by HPC as a lead user and enabled by the CHIPS and Science Act, that can be an organizing principle for future computing research, bridge the valley of death with new public-private partnership models, and address the critical role of workforce development.

Memory Heterogeneity in High Performance Computing Gokcen Kestor | Panel Member November 15, 2022 Panel | 3:30 p.m. – 5 p.m. CST | C147-148-154 Memory heterogeneity refers to the memory architecture with multiple memory components and those memory components have diverse characteristics (such as latency and bandwidth). It is common to see heterogeneous memory (HM) in supercomputers nowadays. With the emergence of processing-in-memory and resource disaggregation, there will be more memory components with increasingly different features (not only in terms of latency and bandwidth, but also in terms of computing capabilities and reliability). Read more.

Exploring FPGA Acceleration of Seed Selection in Influence Maximization Reece Neff | Poster Presenter Marco Minutoli | Contributor Antonino Tumeo | Session Leader Mahantesh Halappanavar | Contributor November 16, 2022 Poster | 8:30 a.m. – 5:00 p.m. | C1-2-3 The Influence Maximization (IM) problem on a social network is the problem of identifying a small cohort of vertices that, when initially activated, results in a cascading effect that will activate the maximum expected number other vertices in the network. While the problem is NP-hard under budget constraints, it has a submodular structure that leads to efficient approximation. In this work, we present techniques and our performance analysis that we are using to drive the design of efficient FPGA acceleration for the seed selection step within the IMM algorithm. Currently, we are able to achieve from 0.75x to 4.78x speedup, with the main bottleneck being a static overhead determined by the size of the input graph. We discuss future work to improve on the current architecture, and hope to provide techniques for making "almost-regular" applications fast and efficient on FPGAs. Read more.

Fifth International Workshop on Emerging Parallel Distributed Runtime Systems and Middleware Joshua Suetterlein | Session Organizer November 18, 2022 Workshop | 8:30 a.m. – 12:00 p.m. CST | C146 The role of runtime and middleware has evolved over the past decades as we have begun the exascale era. For leadership class machines, advanced runtime technology not only plays an important role in tasking but also has gained prominence in providing consistent memory across accelerator architectures, intelligent network routing, and performance portability, among other properties. With diminishing returns from hardware fabrication technology, clusters add more specialized accelerators such as FPGAs, CGRAs, and custom ASICs. These current trends highlight middleware challenges such as task/data management while adding new opportunities for exploiting application-specific engines. Further, advances in fields such as AI/ML provide novel opportunities for guiding and exploiting the hardware/software substrate. For these reasons, we propose a new iteration of the IPDRM workshop which will provide a venue for a diverse group of international researchers from universities, industry, research institutions, and funding agencies to discuss the pressing challenges of today’s runtime/middleware technologies. Read more.

First International Workshop on Cyber Security in High Performance Computing Kevin Barker | Session Chair Joseph Manzano | Session Chair Andres Marquez | Session Chair November 18, 2022 Workshop | 8:30 a.m. – 12:00 p.m. | C141-143-149 As HPC gradually permeates more areas of public interest, in part driven by the 5th paradigm of computing, a hands-off approach to security aspects in favor of performance and power is becoming imprudent at best. Paired with HPC’s traditional role of early technology adoption, a new set of vulnerabilities are emerging that are not necessarily found in other computing scenarios that operate with more established technologies. In addition to early adoption vulnerabilities, the exploits specific to the HPC community arise from acute hardware heterogeneity, novel networks technologies/topologies, massive resource management orchestration, heavy reliance on open software, brittle experimental software, and dusty deck software with a lack of maintenance. We propose a new workshop “S-HPC” that focuses on threats and solutions across the HPC hardware/software stack. These threats include weaknesses in current/future architectural designs, escalation of privileges through data extraction or computation manipulation, intentional misuse of resources across scientific instruments. Read more.

IA^3 2022 - 12th Workshop on Irregular Applications: Architectures and Algorithms John Feo | Session Chair Vito Giovanni Castellana | Session Chair Antonino Tumeo | Session Chair Marco Minutoli | Session Chair November 18, 2022 Workshop | 8:30 a.m. – 12:00 p.m. CST | C144-145 Due to the heterogeneous data sets they process, data intensive applications employ a diverse set of methods and data structures, exhibiting irregular memory accesses, control flows, and communication patterns. Current supercomputing systems are organized around components optimized for data locality and bulk synchronous computations. Managing any form of irregularity on them demands a substantial programming effort, and often leads to poor performance. Holistic solutions to these challenges emerge only by considering the problem from multiple perspectives: from micro- to system-architectures, from compilers to languages, from libraries to runtimes, and from algorithm design to data characteristics. Only collaborative efforts among researchers with different expertise, including domain experts and end users, can lead to significant breakthroughs. This workshop brings together scientists with different backgrounds to discuss methods and technologies for efficiently supporting irregular applications on current and future architectures. Read more.

Petri Nets for Concurrent Programming Michael Rawson | Presenter November 18, 2022 Workshop | 10:55 a.m. – 11:25 a.m. | C146 Concurrent programming is used in all large and complex computer systems. However, concurrency errors and system failures (ex: crashes and deadlocks) are common. We find that Petri nets can be used to model concurrent systems and find and remove errors ahead of time. We introduce a novel generalization of Petri nets with nondeterministic transition nodes to match real systems. These allow for a compact way to construct, optimize, and prove computer programs at the concurrency level. Petri net programs can also be optimized by automatically solving for maximal concurrency, where the maximum number of valid threads is determined by the structure of the Petri net prior to execution. We discuss an algorithm to compute the state graph of a given Petri net start state pair. We introduce our open source software framework which implements this theory as a general purpose concurrency focused middle-ware. Read more.