PNNL

Abstract

As the electronics industry continues to develop higher density circuit board assemblies, manufacturers of multilayer ceramic capacitors (MLCCs) must in turn produce smaller and higher quality devices that meet market needs, i.e. greater capacitance per unit volume of the device. In the multilayer capacitor design this is accomplished by reducing the dielectric and electrode layer thicknesses, allowing manufacturers to incorporate more layers, and therefore more capacitance, into a given volume. However, as the thicknesses of the nickel base metal electrodes (BMEs) currently employed in the majority of MLCCs are reduced to micron-size dimensions, they tend to suffer from intralayer discontinuities or breaks due to microstructural instabilities that arise during the high-temperature sintering step employed in the latter stages of manufacturing. The net effect is that below ~3m in thickness the electrode layers tend to agglomerate, or “island,” during heat treatment, forming defects that can greatly reduce the overall capacitance of the device. Because the dielectric and BME layers are fabricated by powder-based processes, respectively tape casting and screen printing, the mechanisms that control the formation of these intralayer defects are rather complex and can be dependent on a number of processes, including: the differences in the sintering rates of the two materials, the degree of thermal expansion mismatch, potential abnormal grain growth and grain boundary thinning in either layer during co-sintering, and/or de-wetting between the two layers. The study described here addresses the latter in an effort to identify the role that de-wetting might play in the agglomeration phenomenon.