PNNL

Abstract

High-Level Synthesis (HLS) tools simplify the design of hardware accelerators by automatically generating Verilog/VHDL code starting from a general purpose software programming language. They include a wide range of optimization techniques in the process, most of them performed on a low-level intermediate representation (IR) of the code. Introducing optimizations on a higher level of abstraction could significantly contribute to the automated design process results; for example, polyhedral techniques for the manipulation of loops could have a significant impact on the generated accelerators when applied on a specialized IR. We use loop pipelining as a case study to explore the introduction of compiler-based transformations on top of an existing HLS process. We leverage the Multi-Level Intermediate Representation (MLIR) framework and an external scheduler to implement the required transformations, and couple them with existing HLS tools to evaluate the improvements that loop pipelining brings to the performance of generated accelerators. The proposed approach can be integrated with other high-level transformations on the MLIR representation, combining different techniques to obtain pre-optimized inputs for HLS that do not have to rely on a specific backend tool.