May 19, 2021
Conference Paper

Scalable Yet Rigorous Floating-Point Error Analysis

Abstract

Automated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators; barely enough for HPC. In this work, we offer an approach embedded in a new tool called SATIRE that scales error analysis by four orders of magnitude compared to today’s best-of-class tools. We explain how three key ideas underlying SATIRE help it attain such scale: path strength reduction, bound optimization and abstraction. SATIRE provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication and PDE stencils.

Published: May 19, 2021

Citation

Das A., I. Briggs, G. Gopalakrishnan, S. Krishnamoorthy, and P. Panchekha. 2021. Scalable Yet Rigorous Floating-Point Error Analysis. In The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC 2020), November 9-19, 2020, Atlanta, GA, 1-14. Piscataway, New Jersey:IEEE. PNNL-SA-154774. doi:10.1109/SC41405.2020.00055