PNNL

Abstract

The essential aim of spin electronics, or spintronics, is to use the spin of quantum mechanical particles to carry signals and process information. Conventional electronics technology relies on the charges of electrons and holes for this purpose. Signals consist of voltage pulses, each of which is a bundle of charged carriers. Furthermore, conventional digital electronics is classical in nature in that bits are defined in terms of such discrete charge pulses. Here, a "1" bit may be represented by a negative voltage pulse whereas a "0" bit would be the absence of such a pulse. Devices continue to diminish in size in order to achieve higher speeds. As this shrinkage occurs, design parameters are impacted in such a way that the materials in current use are pushed to their limits. As an example from the digital arena, there is Moore's law, which states that the logic density, or amount of storable information per unit area in silicon based integrated circuits doubles every eighteen months. Attempting to keep up with Moore's law has led to the International Technology Roadmap for Semiconductors. This roadmap is aimed specifically at predicting, among other things, how thin the gate oxide must be in order to keep pace with the rate at which lateral dimensions are being reduced in complementary metal oxide semiconductor (CMOS) devices. For a given dielectric constant, the gate thickness must scale with the cross-sectional gate area in order to keep the capacitance constant. As a result of this trend, the main-stay gate oxide of the silicon industry, SiO2, will reach a fundamental limit within a few years because of unacceptably high gate leakage currents that result from the use of SiO2 films of thickness less than ~1.5 nm. Gate leakage results in power dissipation at times other than those when the transistor is changing state, which defeats one of the purposes of CMOS.