This paper presents a comprehensive evaluation of the performance
impact of various Compute Express Link (CXL) memory topologies,
with a particular emphasis on CXL switches, in the context of High-
Performance Computing (HPC) and Large Language Model (LLM)
inference workloads. Our study unveils significant performance
variations across different topologies, demonstrating that certain
configurations yield superior performance for specific workloads.
These findings underscore the critical importance of tailored topol-
ogy selection in optimizing system performance. Additionally, we
address the inherent challenges associated with integrating CXL
switches, including overhead considerations and routing complex-
ities. Our research highlights the necessity for thorough evalua-
tion methodologies to fully leverage CXL technology’s potential
in contemporary computing environments. These insights provide
valuable guidance for system architects and data center operators
in designing and optimizing CXL-based infrastructures for diverse
workload requirements.
Published: February 5, 2025
Citation
Wu J., J. Liu, G. Kestor, R. Gioiosa, D. Li, and A. Marquez. 2024.Performance Study of CXL Memory Topology. In Proceedings of the 10th International Symposium on Memory Systems (MEMSYS 2024), September 30-October 3, 2024, Washington, D.C., 1-6. New York, New York:Association for Computing Machinery.PNNL-SA-203598.doi:10.1145/3695794.3695809