PNNL

Abstract

emember the adage “if it ain’t broke, don’t fix it”? Current computers work, they access memory correctly, my software runs … so why are manufacturers trying to sell me all these new memory types, faster buses, and different chip interconnect protocols? What’s broke? The problem is that multi-core processors are highlighting limitations in the current Front Side Bus (FSB) memory architectures. They really are broken in a performance sense – even though they function correctly. Multi-core processors need fast processor-to-processor communications as well as higher-bandwidth, lower-latency processor-to-memory communications. These needs are driving the adoption of new processor interconnect standards such as Intel’s Common System Interface (CSI) and AMD’s HyperTransport. In the future, it makes sense to avoid that bus.