Thrust 1: Co-design of energy-efficient chiplets

Thrust leads

Tajana Rosing University of California, San Diego	David Brooks Harvard University

Thrust 1 will co-design energy-efficient chiplets. The tasks in Thrust 1 focus on co-designing heterogeneous chiplets based on new computing paradigms and conventional digital computing Intellectual Property (IP) blocks. These tasks include designing analog hyperdimensional computing (from the University of California, San Diego) and Ising machine (from Rice University) accelerators and integrating them with conventional processors, such as central processing units (CPUs), graphics processing units (GPUs), and domain-specific accelerators, to create a highly robust and versatile hardware system capable of addressing DOE’s diverse scientific computing needs. By leveraging both analog and digital accelerators in the co-design flow, we aim to develop heterogeneous architectures that better serve DOE’s energy-efficient computing objectives and improve the hardware-software ecosystem for diverse scientific applications.

Tasks within this thrust are:

Task 1.1: Hyperdimensional computing accelerators

Task leads

Tajana Rosing University of California, San Diego	Partha Pande Washington State University

Task 1.2: Ising machine accelerators

Task leads

Tong (Tony) Geng Rice University	Ang Li Pacific Northwest National Laboratory

Task 1.3: Integration of existing IPs

Task leads

Andreas Olofsson Zero ASIC	David Donofrio Tactical Computing Laboratories