Because they were developed for optimal sequential
complexity, classical graph algorithms as found in textbooks have
strictly-defined orders of operations. Enforcing a prescribed order
of operations, or even an approximate order, in a distributed memory
setting requires significant amounts of synchronization,
which in turn can severely limit scalability. As a result, new
algorithms are typically required to achieve scalable performance,
even for solving well-known graph problems. Yet, even in
these cases, parallel graph algorithms are written according to
parallel programming models that evolved for, e.g., scientific
computing, and that still have inherent, and scalability-limiting,
amounts of synchronization. In this paper we present a new
approach to parallel graph algorithms: synchronization-avoiding
algorithms. To eliminate synchronization and its associated overhead,
synchronization-avoiding algorithms perform work in an
unordered and fully asynchronous fashion in such a way that the
result is constantly refined toward its final state. “Wasted” work is
minimized by locally prioritizing tasks using problem-dependent
task utility metrics. We classify algorithms for graph applications
into two broad categories: algorithms with monotonic updates
(which evince global synchronization) and algorithms with nonmonotonic
updates (which evince vertex-centric synchronization).
We apply our approach to both classes and develop novel,
synchronization-avoiding algorithms for solving exemplar problems:
SSSP and connected components for the former, graph
coloring for the latter. We demonstrate that eliminating synchronization
in conjunction with effective scheduling policies and
optimizations in the runtime results in improved scalability for
both classes of algorithms.
Revised: May 22, 2019 |
Published: December 17, 2018
Citation
Firoz J.S., M.J. Zalewski, T.A. Kanewala, and A. Lumsdaine. 2018.Synchronization-Avoiding Graph Algorithms. In IEEE 25th International Conference on High Performance Computing (HiPC 2018), December 17-20, 2018, Bengaluru, India, 52-61. Los Alamitos, California:IEEE Computer Society.PNNL-SA-138656.doi:10.1109/HiPC.2018.00015