PNNL

Abstract

Designing Field Programmable Gate Array (FPGA) accelerators for complex parallel applications, e.g., graph algorithms, requires hardware design skills different from those typically used in software programming. High-Level Synthesis (HLS) tools can help bridge the gap between hardware and software, but effectively utilizing FPGA resources to generate parallel accelerators is still challenging. This paper presents a methodology for the Synthesis of PARallel multi-Threaded Accelerators (SPARTA), which extends the Bambu HLS tool by synthesizing a custom OpenMP runtime library; the translation of OpenMP pragmas describing parallelism is left to the front-end compiler, and the back-end only has to implement a few low-level function calls. The generated hardware can be integrated with dedicated caches, and it supports context switching of multiple threads on the same accelerator, hiding the latency of memory accesses. Experimental results show excellent parallelization when synthesizing irregular graph applications; the accelerators are, on average, 2.29x faster than the ones generated through a state-of-the-art automated synthesis methodology.