PNNL

Abstract

Counting k-mers (substrings of fixed length k) in DNA and protein sequences generate non-uniform and irregular memory access patterns. Processing-in-Memory (PIM) architectures have potential to significantly reduce the overheads associated with such frequent and irregular memory accesses. However, existing k-mer counting algorithms are not designed to exploit the advantages of PIM architectures. Furthermore, owing to thermal constraints, the allowable power budget is limited in conventional PIM designs. Moreover, k-mer counting generates long-range, non-uniform traffic patterns which needs to be handled by an efficient Network-on-Chip (NoC). In this paper, we present an NoC-enabled hardware/software co-design framework to implement high-performance k-mer counting. The proposed architecture enables more computational power, efficient communication between cores/memory – all without creating a thermal bottleneck. The software component overcomes the I/O bottleneck, aids in NoC design and exposes more in-memory opportunities to exploit in PIM. Experimental results show that the proposed architecture outperforms a state-of-the-art software implementation using Hybrid Memory Cube (HMC), by up to 7.14X, while allowing significantly higher power budget.