Conventional High Level Synthesis (HLS) tools mainly tar- get compute intensive kernels typical of digital signal pro- cessing applications. We are developing techniques and ar- chitectural templates to enable HLS of data analytics appli- cations. These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dy- namic task parallelism. We discuss an architectural tem- plate based around a distributed controller to efficiently ex- ploit thread level parallelism. We present a memory in- terface that supports parallel memory subsystems and en- ables implementing atomic memory operations. We intro- duce a dynamic task scheduling approach to efficiently ex- ecute heavily unbalanced workload. The templates are val- idated by synthesizing queries from the Lehigh University Benchmark (LUBM), a well know SPARQL benchmark.
Revised: June 5, 2018 |
Published: October 1, 2016
Citation
Minutoli M., V.G. Castellana, A. Tumeo, M. Lattuada, and F. Ferrandi. 2016.Enabling the High Level Synthesis of Data Analytics Accelerators. In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES 2016), October 1-7, 2016, Pittsburgh, PA, Article No. 15. New York, New York:ACM.PNNL-SA-119868.doi:10.1145/2968456.2976764