PNNL

Dhruv Gajaria is a postdoctoral research associate in the High-Performance Computing group at Pacific Northwest National Laboratory (PNNL), focusing on hardware-software co-design, advanced memory architectures, and performance analysis. His research addresses critical challenges in computing efficiency and scalability, with a specialization in memory hierarchy modeling, contention analysis, and energy-efficient, domain-specific architectures. Previously, Gajaria explored new paradigms in in-memory computing, leveraging STT-RAM and other advanced non-volatile memory technologies to optimize computing systems for resource-constrained applications. 

Gajaria has contributed to leading journals, including the Institute of Electrical and Electronics Engineers (IEEE) Transactions on Parallel and Distributed Systems and Access journals, and Future Generation Computer Systems. His work has made significant advancements in energy-efficient wearable computing, low-overhead memory contention tools, and high-throughput GPU-based image preprocessing for optical character recognition. As a dedicated mentor, Gajaria has guided students at the University of Arizona, PNNL, and beyond, supporting the next generation of engineers in high-performance computing. 

Gajaria earned his PhD and MS in electrical and computer engineering from the University of Arizona, where his doctoral dissertation focused on STT-RAM-based domain-specific architectures. He holds a BEng in electronics engineering from the University of Mumbai, India. A committed contributor to his field, Gajaria serves as a reviewer for journals such as IEEE Transactions on Computers and participates on technical committees for conferences, including the ACM Great Lakes Symposium on Very Large-Scale Integration (VLSI) and the IEEE Symposium on VLSI.

• C++
• Computing architectures
• Embedded systems
• Energy-efficient computing
• High-performance computing
• Modeling and simulation
• Performance analysis
• Machine learning
• Python
• VLSI design
• Workload characterization

• PhD in electrical and computer engineering, University of Arizona
• MS in electrical and computer engineering, University of Arizona
• BS in electronics, University of Mumbai

• IEEE
• Association for Computing Machinery

• Travel Grant, National Science Foundation, 2022
• People's Choice Award Runner Up, Graduate Student Research Poster Symposium, University of Arizona, 2022
• Outstanding Graduate Teaching Assistant, Electrical and Computer Engineering Department, University of Arizona, 2020 – 2021

2024

• Gajaria D., T. Adegbija and K. Gomez. 2024. "CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing," 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Hong Kong, pp. 228-236, doi:10.1109/ASAP61560.2024.00053
• Gajaria D., K. A. Gomez and T. Adegbija. 2024. "STT-RAM-Based Hierarchical in-Memory Computing," in IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 9, pp. 1615-1629. doi:10.1109/TPDS.2024.3430853
• Yusuf A., T. Adegbija and D. Gajaria. 2024. "Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey," in IEEE Access, vol. 12, pp. 28036-28056. doi:10.1109/ACCESS.2024.3365632

2023

• Gener S., P. Dattilo, D. Gajaria et al. 2023. “GPU-based and Streaming-enabled Implementation of Pre-processing Flow towards Enhancing Optical Character Recognition Accuracy and Efficiency,” Research Square, preprint. doi:10.21203/rs.3.rs-3097904/v1

2022

• Gajaria D., T. Adegbija. 2022. “Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads,” Future Generation Computer Systems, Volume 136, Pages 231-240, doi:10.1016/j.future.2022.05.023
• Gajaria D., T Adegbija. 2022. “Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing,” Journal of Signal Processing Systems 94, 559–577. doi:10.1007/s11265-021-01682-y
• Gener S., P. Dattilo, D. Gajaria, A. Fusco and A. Akoglu. 2022. "GPGPU-based High Throughput Image Pre-processing Towards Large-Scale Optical Character Recognition," 2022 IEEE/ACS 19th International Conference on Computer Systems and Applications (AICCSA), Abu Dhabi, United Arab Emirates, pp. 1-7, doi:10.1109/AICCSA56895.2022.10017481
• Gajaria D., K.A. Gomez, T. Adegbija. 2022. “A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy,” Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Volume 2022-October, Pages 685 – 692, doi:10.1109/ICCD56317.2022.00105

2020

• Cordeiro R., D. Gajaria, A. Limaye, T. Adegbija, N. Karimian and F. Tehranipoor. 2020. "ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 11, pp. 3373-3384, doi:10.1109/TCAD.2020.3012169

2019

• Gajaria D. and T. Adegbija. 2019. “ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors.” In Proceedings of the International Symposium on Memory Systems (MEMSYS '19), Association for Computing Machinery, New York, NY, USA, 439–450. doi:10.1145/3357526.3357553
• Gajaria D., K. Kuan and T. Adegbija. 2019. "SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning," 2019 Tenth International Green and Sustainable Computing Conference (IGSC), Alexandria, VA, USA, pp. 1-7, doi:10.1109/IGSC48788.2019.8957182