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Three major Labs join forces to develop faster semiconductors

Oak Ridge National Laboratory, Motorola Labs and Pacific Northwest National Laboratory enter cooperative research agreement to pursue new materials

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May 15, 2001 Share This!

RICHLAND, Wash. — Scientists at Oak Ridge National Laboratory (ORNL), Motorola Labs, and Pacific Northwest National Laboratory (PNNL) have entered a cooperative research and development agreement (CRADA) aimed at increasing the speed of future generations of integrated circuits.

Together, the scientists will pursue new materials that they believe may overcome a fundamental physics problem that threatens to limit future semiconductor improvements, and for which the semiconductor industry currently has no solution.

For decades, the semiconductor industry has been able to continue increasing the amount of circuitry, or computing power, on a chip while reducing its size-enabling smaller, faster and better electronic products. However, researchers have long known that the industry will eventually hit a wall that will prevent semiconductor designers from achieving additional size reduction.

The problem lies with the current gate insulating material, a layer of silicon dioxide approximately 35 angstroms thick, or the thickness of 25 individual silicon atoms. The silicon dioxide layer "gates" the electrons, controlling the flow of electricity across the transistor. Each time the chip is reduced in size, the silicon dioxide layer must also be proportionally thinned. At the current pace of chip progression, industry experts expect the gate thickness will need to be reduced to fewer than 10 angstroms in the next ten years. Unfortunately, once the thickness is reduced to 20 angstroms or less (anticipated later next year), the silicon dioxide is no longer able to provide effective insulation from the effects of quantum tunneling currents and the devices will fail to work properly. Quantum tunneling refers to the natural tendency of electrons to flow across thin barriers or thin insulators.

To develop an effective gate insulator at a dimension of fewer than 20 angstroms, most industry experts predict the need to develop new materials with a higher dielectric constants (sometimes referred to as high-k materials) that have a higher capacitance for a given thickness. Independent of each other, ORNL and Motorola Labs have been developing just such materials in the form of crystalline oxides on silicon and other semiconductor materials.

"By using crystalline oxides, we're able to eliminate one of the hurdles to continuing the current rate of growth in the semiconductor industry," said Rodney McKee of ORNL's Metals and Ceramics Division. The work of McKee and colleague Fred Walker, addresses the transistor gate-the dielectric layer that controls the flow of electricity through the transistor. "This is a great example of how Department of Energy-funded basic science research could have a significant impact on a major U.S. industry," Walker said.

Motorola Labs also has been researching high-k materials for several years and, in 1999, demonstrated the world's thinnest functional transistor by growing a strontium titanate crystalline material on a silicon substrate. This high-k material demonstrated electrical properties more than 10 times better than equivalent silicon dioxide.

While both labs have made significant progress independently, the scientists hope that combining their expertise will enable them to solve more quickly the remaining issues for the benefit of the entire U.S. semiconductor industry.

"Both ORNL and Motorola Labs have made promising progress in the past few years, and we are looking forward to evaluating the specifics of ORNL's technology," said Bill Ooms, director of Materials, Device, and Energy Research within Motorola Labs. "Motorola Labs has already been working with PNNL to evaluate the samples grown at Motorola, and they will bring to the project an important expertise in understanding the growth mechanism and structural and electronic properties of the semiconductor-oxide interface."

The three-year research agreement has two phases. The first phase, expected to take one year, will address transferring the details of ORNL's patented crystalline oxide on silicon process to Motorola Labs and PNNL. The second phase includes testing and optimizing the technology to ensure that the critical performance and processing issues required for aggressively scaled alternative gate silicon technology can be met. Motorola Labs will evaluate the technology and, if it proves workable, may implement and tailor the technology to Motorola-specific needs.

Tags: Energy

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